The present invention relates to a semiconductor memory device, such as a static RAM (random access memory) having initialization function.
An example of prior-art memory of this type is shown in Japanese Patent Application Kokai Publication No. 37442/1988. In this prior art scheme, all the memory cells are initialized simultaneously. A disadvantage arising from this scheme is that bit lines must be set to the ground potential and therefore the control for the initialization is complex. Moreover, excessive currents may flow through the bit lines when all the memory cells are simultaneously initialized, and the bit lines may be damaged by fusiondisconnection.
In another prior art, the row address decoder is used to sequentially select the word lines to write "0". This prolongs the time required for the initialization.